Low Power Double Data Rate 4



Feature List

  • 16n prefetch architecture with 256 bits per memory read and write access
  • Differential clock inputs (CK_t/CK_c)
  • BL = 16 and 32
  • 16 DQ width
  • Bank Grouping supported
  • 2K or 4K Bytes per page; varies by device density/channel
  • 64 bit prefetch boundary
  • 2 independent channel per device

azLPDDR4 Features

  • Data mask for masking WRITE data per byte
  • Self Refresh Modes
  • Channel density of 4Gb to 32Gb per Die.
  • DDR commands entered on each positive CK_t, CK_c edge. All other commands are one cycle command.
  • Independent Command Interfaces allowing to be issued in parallel with Read/Writes in separate channels.
  • 8 banks per channel; varies by device density/channel
  • Auto precharge, auto refresh supported.
  • Download Datasheet